`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:20:50 12/03/2010 
// Design Name: 
// Module Name:    mux 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module mux
	#(parameter N=8)
(
  input wire [1:0] sel,
  input wire [N-1:0] in0,
  input wire [N-1:0] in1,
  input wire [N-1:0] in2,
  input wire [N-1:0] in3,
  output reg [N-1:0] out
);

	always @*
		case (sel)
			2'b00:
				out <= in0;
			2'b01:
				out <= in1;
			2'b10:
				out <= in2;
			2'b11:
				out <= in3;
		endcase

endmodule
